Recently, the gate size of devices in CMOS technology has been reduced to less than 100 nm, and devices for high-speed logic and memory applications have been actively developed. In MOS devices for logic applications, the thickness of a gate insulating film can be reduced to 2 nm or less, and thus so-called short-channel effect can be suppressed. The MOS devices can be applied in various fields such as CPU and logic, although they have some short-channel effects.
However, in DRAM applications, the thickness of the gate insulating film must be at least 5 nm. Although this thickness can decrease according to the development of technology in future, it will be difficult to decrease greatly. Thus, since the gate insulating film in MOS devices for DRAM application can be reduced only to a limited extent as compared to that in devices for logic applications, the existing MOS devices having a planar channel have a severe short-channel effect.
One of methods capable of solving this problem is to recess a channel region. In the structure having the recessed channel region, the short-channel effect can be improved as compared to the existing planar channel MOS devices. Also, the sensitivity of threshold voltage to the doping concentration or profile of corner regions formed at the bottom of the recessed channel are very high, even when the corner regions are made round. Furthermore, in these recessed devices, a change in threshold voltage due to substrate bias is much greater than in the existing planar channel structure, and the effective channel length is increased due to the channel recess. Thus, the recessed structures have a shortcoming in that, if the channel width becomes narrower, the current drivability will be greatly reduced. The general feature of the recessed channel devices is that the gate electrode is inferior in its ability to control the channel to that in the planar channel devices. This is associated with a large substrate bias effect.
The case where a gate electrode is excellent in its ability to control a channel is a double/triple-gate MOS structure, in which the gate wraps the channel region. The present inventors developed, for the first time in the world, a body-tied double/triple-gate MOS structure (Korean Patent Application No. 2002-5325, Japanese Patent Application No. 2003-298051, and U.S. patent application Ser. No. 10/358,981) and the application thereof to flash memories (Korean Patent Registration No. 0420070 and U.S. patent application Ser. No. 10/751,860, and named this structure “bulk FinFET”.
In this structure, the channel is not recessed, and is formed either on the surface and both sides of the active body or on both sides of the body, so that the structure is much superior in the ability of the gate to control the channel to the existing planar channel devices, and has a very small substrate bias effect. However, in order to suppress the short-channel effect, the body width must be about ⅔ of physical gate length. This means formation of a silicon body having a width narrower than the minimum gate length, causing a process problem.
Meanwhile, the existing planar channel MOS devices with a gate length of less than 100 nm show various problems in scaling down. It is reported that the existing planar channel device can be currently scaled down to a gate length of less than 50 nm, and the scaling down of the existing planar channel device structure encounters the problem of so-called short-channel effect. Generally, with the scaling-down of devices, the thickness of the gate insulating film can also be reduced, and thus the short-channel effect can be suppressed partly. In MOS devices for logic applications, the thickness of the gate oxide film can be reduced to less than 2 nm, so that the short-channel effect resulting from a reduction in the gate length can be somewhat suppressed. MOS devices having a little short-channel effect can be used for logic circuit applications.
With the scaling down of MOS devices for logic applications, the channel length of devices for dynamic random access memory (DRAM) applications decreases to less than 70 nm, while these devices encounter larger difficulty in scaling down than those for logic applications. In MOS devices for DRAM applications, since the thickness of the gate insulating film is generally about 5 nm or thinner, the above-mentioned short-channel effect is not effectively suppressed. If the operating voltage of DRAM and the thickness of the gate insulating film are reduced at a given gate length, the scaling-down at a gate length of less than 70 nm seems likely to be possible. However, according to general scaling rule, the scaling down of DRAM devices with conventional planar channel structure seems to be difficult, and a change in device structure to solve this difficulty is required.
A case where a device, fabricated by simply etching a channel to make a recessed channel and forming a gate insulating film and then a gate electrode is applied to DRAM, was proposed by Samsung Electronics Co. in the year 2003 (J. Y. Kim et al., “The breakthrough in data retention time of DRAM using recess-channel-array transistor (RCAT) for 88 nm feature size and beyond”, in Proc. Symp. on VLSI Tech., p. 11, 2003).